Timing-rearrangements of SEC and SASE slave clock chains due to non-small input phase and frequency hits in synchronization networks

In synchronization networks, chains of slave clocks (viz. SASE, SEC) transfer timing along synchronization trails. Hence, the need to assess precisely the performance of timing transfer along such chains, not only in stationary conditions, but also under transient rearrangements occurring after phase and frequency hits on the tuning reference. In this work, the non-linear transient behavior of SEC and SASE clock chains has been simulated in the time domain, in order to evaluate their timing rearrangements after non-small phase and frequency hits on the reference. Both homogeneous and non-homogeneous chains of SEC and SASE clocks have been studied in various configurations, in order to provide synchronization engineers with a comprehensive survey, both in qualitative and quantitative terms, on the timing performance achievable when planning synchronization trails of various type and length.