Cause of erase speed degradation during two-bit per cell operation of a trapping nitride storage flash memory cell

Erase speed degradation in a dual-bit, trapping nitride storage flash memory cell is investigated. Our study shows that the trapped-electron area of the second-programmed bit would extend more toward the central channel region if its neighboring bit (of the same cell) has been programmed. The second bit would then be erased slower. This effect gets more obvious after program/erase cycling. In addition, the erase speed would be modulated by adjacent junction biases in a short-channel, nearly punch-through cell.