Drop impact reliability analysis of CSP packages at board and product system levels through modeling approaches

Chip Scale Package (CSP) and fine pitch Ball Grid Array (BGA) packages have been increasingly used in portable electronic products such as mobile cell phones and PDA, etc. Drop impact which is inevitable during its usage could cause not only housing crack but also package to board interconnect failure, such as BGA solder breaks. Various drop tests have been used to ensure high reliability performance of packaging to withstand such impact and shock load. It will be beneficial through modeling techniques using Finite Element Analysis tool to better understand the dynamic characterization of a package under different drop loads to avoid extensive physical testing cost as well as its repeatability challenge. In this paper, three drop tests have been modeled, namely, bare board drop, board with fixture drop/shock, and system level phone drop. Submodeling and explicit-implicit sequential modeling techniques are used to investigate the dynamic characterization of CSP packages in both PCB board and BGA solder joints which include failure criteria, effects of strain rate and edge support in multi-component boards. A validation test with data acquisition is also used to correlate the test results with numerical results.