Thermal analysis and modeling of diode array integrated with directional liquid-cooled heat sink

The thermal analysis and modeling of diode arrays integrated with directional liquid-cooled heat sinks are presented. The heat sink under consideration is made of copper with varying channel and fin widths. Established analysis and simulation models show that a heat sink with channel and fin widths of 0.2 mm provide acceptable pressure drop less than 5 bar, resulting in a heat sink thermal resistance of 0.0128°C/W. In the package level analysis, the emitters are modeled in three ways: heat source lumped in the diode volume, heat source lumped in the emitter volume and concentrated heat source at the active layer. The last modeling gives the highest junction temperature with the heat sink cooling and the lowest junction to ambient thermal resistance of 0.0459°C/W, indicating a heat flux of 300W/cm² for a given junction temperature constraint of 80°C. The thermal resistance network analysis shows that 29% of thermal resistance is due to the heat sink whereas the major portion arises from the package. An analytical solution is also developed to investigate the heat source modeling on the estimation of the maximum junction temperature of tile emitter. The junction temperature is found to increase with the decrease in the heat source size, although insignificantly, and approaches an asymptotic maximum when the heat source size shrinks to an infinitesimal value.