DocumentCode :
41595
Title :
Test Compaction by Sharing of Transparent-Scan Sequences Among Logic Blocks
Author :
Pomeranz, Irith
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Volume :
22
Issue :
4
fYear :
2014
fDate :
Apr-14
Firstpage :
792
Lastpage :
802
Abstract :
An approach to test application called transparent scan provides an opportunity to share tests among different logic blocks whose primary inputs and outputs are included in scan chains even if the blocks have different numbers of state variables. A transparent-scan sequence for one block is likely to detect faults in other blocks since transparent scan does not distinguish between functional and scan clock cycles, and allows faults to be detected at all the clock cycles of the sequence. Such sharing of tests is not meaningful with conventional scan-based tests, especially when the blocks have different numbers of state variables. Transparent scan thus enhances the ability to produce a compact test set for a group of logic blocks. The static test compaction procedure described in this paper uses transparent-scan sequences that follow the application of conventional scan-based tests precisely. The procedure obtains a set of transparent-scan sequences for a group of logic blocks from compacted test sets for the logic blocks in the group. From this set, it selects a subset that detects all the target faults, which are detected by the complete set.
Keywords :
logic testing; functional clock cycle; logic blocks; scan based tests; scan chains; scan clock cycle; static test compaction; transparent scan sequence; Full-scan circuits; test compaction; test generation; transparent scan;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/TVLSI.2013.2256438
Filename :
6510481
Link To Document :
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