High speed DDR performance in 4 vs 6 layer FCBGA package design

Author

Chan, Edward ; Chen, Huabo ; Chung, Chee Yee

Author_Institution

NVIDIA Corp., Santa Clara, CA, USA

Volume

1

fYear

2004

fDate

1-4 June 2004

Firstpage

314

Abstract

This is a comparative study of the performance of 4-layer and 6-layer FCBGA packages designed to support a high speed DDR1 (double-data rate) interface. Being able to quantify the performance impact in terms of MHz is critical to help decide the cost vs. performance trade-off. A detailed simulation approach, where we were able to translate power distribution network performance into timing impact, is presented. The good correlation between simulations and measurements demonstrates our ability to predict performance and helps improve future decisions based on tradeoffs between cost and performance.

Keywords

ball grid arrays; flip-chip devices; integrated circuit modelling; integrated circuit packaging; system buses; cost/performance trade-off; double-data rate wide-bus; flip chip ball grid array packages; high speed DDR1 interface; high-speed signalling interface; memory I/O interface; multilayer FCBGA package; power distribution network timing effects; Capacitors; Costs; Crosstalk; Electronics packaging; Flowcharts; Power systems; Predictive models; Resists; Routing; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Components and Technology Conference, 2004. Proceedings. 54th

Print_ISBN

0-7803-8365-6

Type

conf

DOI

10.1109/ECTC.2004.1319357

Filename

1319357