Title :
Board level reliability study on three-dimensional thin stacked package
Author :
Kim, Jin-young ; Kang, Won-Joon ; Ka, Yoon-Hyun ; Kim, Yong-Joon ; Sohn, Eun-Sook ; Park, Sung-Su ; Kim, Jae-Dong ; Lee, Choon-Heung ; Yoshida, Akito ; Syed, Ahmer
Author_Institution :
R&D Center, Amkor Technol. Korea Inc., Seoul, South Korea
Abstract :
This paper discusses the optimal design for PS-etCSP to achieve reliable thermal fatigue life of solder joint. For this purpose design analysis was performed using both simulation and experimental approaches. Since reduction of warpage is most critical issue to ensure good solder joint connection for thin packages, parametric study was performed to find the optimal set of package outline dimensions using finite element method. Next to find the optimal design far solder joint reliability, 3D FEA fatigue model was established with non linear material properties of solder joint. Various factors such as ball land size, motherboard thickness and surface mounting type were studied. As a result, it is found that thin die with small size and small CTE molding compound is better for minimizing package warpage and larger opening size, thinner board and single mounting on board are good for solder joint reliability. The stack of package however has little effect on solder joint reliability. The effects of board thickness and surface mounting type (single/double) were investigated in terms of assembly stiffness and solder joint reliability. Simulation results showed good correspondence with experiment. The fatigue life and failure location predicted by simulation agreed well with experimental data. The fatigue life of optimal design was 1225 cycles for single PS-etCSP and 990 cycles for stacked PS-etCSP with single side mounting on board under the thermal cycling loading of temperature of -40°C∼125°C. Subsequently it can be concluded that optimal design of PS-etCSP can meet the requirement for most portable product applications.
Keywords :
chip scale packaging; circuit simulation; deformation; failure analysis; finite element analysis; integrated circuit modelling; integrated circuit reliability; integrated circuit testing; soldering; thermal stress cracking; -40 to 1250 C; 3D FEA fatigue model; 3D thin stacked package; PS-etCSP; assembly stiffness; ball land size; board level reliability; board thickness; design analysis; die size; extremely thin chip scale package; failure location; fatigue life; finite element method; molding compound CTE; motherboard thickness; opening size; optimal design; package outline dimensions; package stack; package warpage; portable product applications; reliable thermal fatigue life; simulation; single PS-etCSP; single mounting on board; single side mounting; solder joint; solder joint connection; solder joint reliability; stacked PS-etCSP; surface mounting type; thermal cycling loading; warpage reduction; Analytical models; Fatigue; Finite element methods; Land surface; Material properties; Materials reliability; Packaging; Parametric study; Performance analysis; Soldering;
Conference_Titel :
Electronic Components and Technology Conference, 2004. Proceedings. 54th
Print_ISBN :
0-7803-8365-6
DOI :
10.1109/ECTC.2004.1319403