DocumentCode :
416020
Title :
Qualification of SnAg solder bumps for lead-free flip chip applications
Author :
Ebersberger, Bernd ; Bauer, Robert ; Alexa, Lars
Author_Institution :
Infineon Technol. AG, Munich, Germany
Volume :
1
fYear :
2004
fDate :
1-4 June 2004
Firstpage :
683
Abstract :
Lead-free solder bumps as first level flip chip interconnections are still new to the semiconductor industry. Before products can confidently use this new material extensive qualification tests have to be performed to ensure that the bumps meet all requirements. The latter relate both to the subsequent flip chip assembly process and to the reliability of the interconnections under product specific operating conditions. Reliability tests have to take into account all kinds of stress that can lead to degradation of the solder bump interconnects and reduce their lifetime. The results obtained from these tests allow us to set the application range for the electroplated SnAg bumps that are investigated here. Bump quality and homogeneity was assessed on wafer level by optical inspection and shear tests. Reliability after various stress conditions, mainly determined by temperature and electric current, was checked on wafer level but mostly on the assembled system including chip pad and substrate pad. The assembled bumps were studied using electric resistance measurements and physical analysis. Results obtained from the various tests give evidence of the high maturity of these lead-free bumps, which would allow them to replace eutectic SnPb in most applications.
Keywords :
electric resistance; electroplated coatings; flip-chip devices; inspection; integrated circuit interconnections; integrated circuit packaging; integrated circuit reliability; shear strength; silver alloys; soldering; solders; thermal stresses; tin alloys; SnAg; SnAg solder bump qualification; SnPb; assembled bumps; bump homogeneity; bump quality; electric current stress; electric resistance measurements; electroplated SnAg bumps; eutectic SnPb replacement applications; first level flip chip interconnections; flip chip assembly process; interconnection degradation; lead-free flip chip applications; optical inspection; physical analysis; product specific operating conditions; qualification tests; reliability tests; semiconductor industry; shear tests; solder bump lifetime; stress conditions; temperature stress; wafer level tests; Assembly; Electronics industry; Environmentally friendly manufacturing techniques; Flip chip; Lead compounds; Materials testing; Performance evaluation; Qualifications; Semiconductor materials; Stress;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Components and Technology Conference, 2004. Proceedings. 54th
Print_ISBN :
0-7803-8365-6
Type :
conf
DOI :
10.1109/ECTC.2004.1319412
Filename :
1319412
Link To Document :
بازگشت