Damage mechanics of electronics on metal-backed substrates in harsh environments

In this study, the effect of metal-backed boards on the interconnect reliability has been evaluated. Previous studies on electronic reliability for automotive environments have addressed the damage mechanics of solder joints in plastic ball-grid arrays on non-metal backed substrates (Lall et al., 2003, Syed et al., 1996, Evans et al., 1997, Mawer et al., 1999) and ceramic BGAs on non-metal backed substrates (Darveaux et al., 1992, 1995, 2000). Other failure mechanisms investigated include delamination of PCB from metal backing. Increased use of sensors and controls in automotive applications has resulted in significant emphasis on the deployment of electronics directly mounted on the engine and transmission. Increased shock, vibration, and higher temperatures necessitate the fundamental understanding of damage mechanisms which are active in these environments. Electronics typical of benign office environments uses FR-4 printed circuit boards. Automotive application typically use high glass-transition temperature laminates such as FR4-06 glass/epoxy laminate material (T_g=164.9°C). In application environments, metal-backing of printed circuits boards is being targeted for thermal dissipation, mechanical stability and interconnections reliability. The test vehicle is a metal backed FR4-06 laminate. The printed circuit board has an aluminum metal backing, attached with pressure sensitive adhesive (PSA). Component architectures tested include plastic ball grid array devices, C2BGA devices, QFN, and discrete resistors. Reliability of the component architectures has been evaluated for HASL. Crack propagation and intermetallic thickness data has been acquired as a function of cycle count. Reliability data has been acquired on all these architectures. Material constitutive behavior of PSA has been measured using uniaxial test samples. The measured constitutive behavior has been incorporated into non-linear finite element simulations. Predictive models have been developed for the dominant failure mechanisms for all the component architectures tested.