Design and analysis methodologies of a 6.4 Gb/s memory interconnect system using conventional packaging and board technologies

In this paper, the design, modeling, and analysis methodologies used to develop a 64 Gb/s memory interconnect system using conventional interconnect technologies are presented. The traditional design and development process of the high-speed memory system remains valuable for multi-Gigabit system design. However, the uncertainty in time and voltage of conventional circuit simulation tools can be a significant portion of the bit time and voltage swing, respectively. Therefore, improved modeling and simulation methodologies that are based on fullwave electromagnetic and hardware correlations are a critical part of predicting the performance and verifying the robustness of multi-GHz interconnect systems. The design, modeling and characterization of an XDR system operating at 6.4 Gb/s data rates are presented. The improved modeling and measurement techniques are described. To illustrate the validity of the proposed modeling methodologies, channel models are correlated with actual hardware at both component and system levels in both time and frequency domains. Finally, effects of a simple preemphasis equalization technique are also analyzed.