Wafer level interconnects for 3D packaging

Author

Banerjee, S.R. ; Drayton, Rhonda Franklin

Author_Institution

Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA

Volume

2

fYear

2004

fDate

1-4 June 2004

Firstpage

1513

Abstract

A hybrid electrical package is compared to monolithic designs to isolate the effects of wirebond parasitics and modularity. The monolithic designs produce 3.2 dB of insertion loss at 50 GHz, which indicates minimal loss due to wirebonds. The hybrid design insertion loss is within 0.5 dB of the reference case up to 40 GHz. The response is oscillatory above this frequency due to complex substrate transitions. Quasi-static modeling techniques are also used to model the wirebond effects with standard CAD tools.

Keywords

circuit CAD; hybrid integrated circuits; integrated circuit design; integrated circuit interconnections; integrated circuit measurement; integrated circuit modelling; integrated circuit packaging; lead bonding; losses; 3.2 dB; 3D packaging; 40 GHz; 50 GHz; CAD tools; hybrid design insertion loss; hybrid electrical package; insertion loss; modularity; monolithic designs; oscillatory response; quasi-static modeling techniques; substrate transitions; wafer level interconnects; wirebond effects model; wirebond loss; wirebond parasitics; Frequency; Insertion loss; Integrated circuit interconnections; Integrated circuit packaging; Integrated circuit synthesis; Integrated circuit technology; Isolation technology; Microstrip; Signal design; Wafer scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Components and Technology Conference, 2004. Proceedings. 54th

Print_ISBN

0-7803-8365-6

Type

conf

DOI

10.1109/ECTC.2004.1320315

Filename

1320315