DocumentCode
416190
Title
Designing of precomputational-based low-power Viterbi decoder
Author
Yang, Jing-ling ; Wong, Alfred K K
Author_Institution
Dept. of Electr. & Electron. Eng., Hong Kong Univ., China
Volume
2
fYear
2004
fDate
31 May-2 June 2004
Firstpage
603
Abstract
This work addresses the low-power VLSI implementation of the Viterbi decoder (VD). A new precomputational scheme applied to the trellis butterflies calculation is presented. The proposed scheme is implemented in a 16-state, rate 1/3 VD. Gate-level power verification indicates that the proposed design reduces the power dissipated by the original trellis butterflies calculation by 42%.
Keywords
VLSI; Viterbi decoding; hypercube networks; low-power electronics; trellis codes; gate-level power verification; low-power VLSI implementation; power dissipation; precomputational-based low-power Viterbi decoder; trellis butterflies calculation; Convolution; Convolutional codes; Decoding; Energy consumption; Feedback loop; Power engineering and energy; Signal processing algorithms; Throughput; Very large scale integration; Viterbi algorithm;
fLanguage
English
Publisher
ieee
Conference_Titel
Emerging Technologies: Frontiers of Mobile and Wireless Communication, 2004. Proceedings of the IEEE 6th Circuits and Systems Symposium on
Print_ISBN
0-7803-7938-1
Type
conf
DOI
10.1109/CASSET.2004.1321960
Filename
1321960
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