• DocumentCode
    416213
  • Title

    Design and reliability challenges in nanometer technologies

  • Author

    Borkar, S. ; Karnik, T. ; Vivek De

  • Author_Institution
    Intel Labs, Hillsboro, OR
  • fYear
    2004
  • fDate
    7-11 July 2004
  • Firstpage
    75
  • Lastpage
    75
  • Abstract
    CMOS technology scaling is causing the channel lengths to be sub-wavelength of light. Parameter variation, caused by sub-wavelength lithography, will pose a major challenge for design and reliability of future high performance microprocessors in nanometer technologies. In this paper, we present the impact of these variations on processor functionality, Predictability and reliability. We propose design and CAD solutions for variation tolerance. We conclude this paper with sofi error rate scaling trends and sofl error tolerant circuits for reliabilitv enhancement.
  • Keywords
    CMOS technology; Circuit testing; Design automation; Error analysis; Fault tolerance; Frequency; Leakage current; Lithography; Microprocessors; Random access memory;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 2004. Proceedings. 41st
  • Conference_Location
    San Diego, CA, USA
  • ISSN
    0738-100X
  • Print_ISBN
    1-51183-828-8
  • Type

    conf

  • Filename
    1322441