Reliable communication in systems on chips

System on Chip (SoC) design faces several challenges which are due to the extremely small nature of electronic devices and the consequent opportunity to realize multi-processing systems of extremely high complexity. To manage large scale design, SoCs are assembled out of complex standard parts, such programmable cores and memory arrays. Thus, the major design challenge is to provide correct and reliable operation of the interconnected components. Topdown correct component interconnection will become increasingly harder to succeed, because the interface features of components will also scale-up in complexity. New design methodologies will need to leverage component self-configuration and adaptation to the underlying communication fabric.