DocumentCode :
416233
Title :
Buffer sizing for clock power minimization subject to general skew constraints
Author :
Kai Wang ; Marek-Sadowska, M.
Author_Institution :
University of California, USA
fYear :
2004
fDate :
7-11 July 2004
Firstpage :
159
Lastpage :
164
Keywords :
Analytical models; Clocks; Delay effects; Permission; Power dissipation; Routing; Scheduling algorithm; Taylor series; Time domain analysis; Wire;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2004. Proceedings. 41st
Conference_Location :
San Diego, CA, USA
ISSN :
0738-100X
Print_ISBN :
1-51183-828-8
Type :
conf
Filename :
1322462
Link To Document :
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