DocumentCode :
416280
Title :
A method to decompose multiple-output logic functions
Author :
Sasao, Tsutomu ; Matsuura, Munehiro
Author_Institution :
Kyushu Institute of Technology, Japan
fYear :
2004
fDate :
7-11 July 2004
Firstpage :
428
Lastpage :
433
Keywords :
Adders; Algorithm design and analysis; Binary decision diagrams; Circuits; Delay; Field programmable gate arrays; Input variables; Logic design; Logic functions; Table lookup;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2004. Proceedings. 41st
Conference_Location :
San Diego, CA, USA
ISSN :
0738-100X
Print_ISBN :
1-51183-828-8
Type :
conf
Filename :
1322519
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=416280
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