A methodology to improve timing yield in the presence of process variations

Author

Raj, Sreeja ; Vrudhula, Sarma B K ; Wang, Janet

Author_Institution

ECE Dept., University of Arizona

fYear

2004

fDate

7-11 July 2004

Firstpage

448

Lastpage

453

Keywords

Circuits; Delay; Design methodology; Fabrication; Low power electronics; Random variables; Size control; Timing; Uncertainty; Yield estimation;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2004. Proceedings. 41st

Conference_Location

San Diego, CA, USA

ISSN

0738-100X

Print_ISBN

1-51183-828-8

Type

Filename

1322523

Link To Document