A method for correcting the functionality of a wire-pipelined circuit

Author

Nookala, Vidyasagar ; Sapatnekar, Sachin S.

Author_Institution

University of Minnesota, Minneapolis, MN

fYear

2004

fDate

7-11 July 2004

Firstpage

570

Lastpage

575

Keywords

Circuit testing; Clocks; Delay; Flip-flops; Frequency; Integrated circuit interconnections; Permission; Pipeline processing; Throughput; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2004. Proceedings. 41st

Conference_Location

San Diego, CA, USA

ISSN

0738-100X

Print_ISBN

1-51183-828-8

Type

Filename

1322547

Link To Document