Title :
Architecture-level synthesis for automatic interconnect pipelining
Author :
Cong, Jason ; Fan, Yiping ; Zhang, Zhiru
Author_Institution :
University of California, Los Angeles, CA
Keywords :
Algorithm design and analysis; Clocks; Delay effects; Flip-flops; Frequency; Integrated circuit interconnections; Permission; Pipeline processing; Wires; Wiring;
Conference_Titel :
Design Automation Conference, 2004. Proceedings. 41st
Conference_Location :
San Diego, CA, USA
Print_ISBN :
1-51183-828-8
