Title :
Floorplanning optimization with trajectory piecewise-linear model for pipelined interconnects
Author :
Changbo Long ; Simonson, Lucanus J. ; Liao, Weiping ; He, Lei
Author_Institution :
University of California, Los Angeles, CA
Keywords :
Algorithm design and analysis; Clocks; Delay; Integrated circuit interconnections; Microprocessors; Permission; Piecewise linear techniques; Pipeline processing; System performance; Wire;
Conference_Titel :
Design Automation Conference, 2004. Proceedings. 41st
Conference_Location :
San Diego, CA, USA
Print_ISBN :
1-51183-828-8
