Title :
Post-layout logic optimization of domino circuits
Author :
Cao, Aiqun ; Koh, Cheng-Kok
Author_Institution :
Purdue University, West Lafayette, IN
Keywords :
Algorithm design and analysis; CMOS logic circuits; Circuit synthesis; Costs; Delay; Integrated circuit synthesis; Logic circuits; Logic design; Pulse inverters; Timing;
Conference_Titel :
Design Automation Conference, 2004. Proceedings. 41st
Conference_Location :
San Diego, CA, USA
Print_ISBN :
1-51183-828-8
