Title :
A novel technique to improve noise immunity of CMOS dynamic logic circuits
Author :
Ding, Li ; Mazurnder, P.
Author_Institution :
University of Michigan, Ann Arbor
Keywords :
CMOS logic circuits; Circuit noise; Circuit testing; Integrated circuit reliability; Logic circuits; Logic design; Logic gates; Noise level; Threshold voltage; Very large scale integration;
Conference_Titel :
Design Automation Conference, 2004. Proceedings. 41st
Conference_Location :
San Diego, CA, USA
Print_ISBN :
1-51183-828-8
