DocumentCode :
417041
Title :
Design of a parallel VLSI processor for tele-robot systems based on dynamic reconfiguration of power supply voltages
Author :
Fujioka, Y. ; Tomabechi, N. ; Kameyama, M.
Author_Institution :
Hachinohe Inst. of Technol., Japan
Volume :
2
fYear :
2003
fDate :
4-6 Aug. 2003
Firstpage :
1978
Abstract :
To improve the responsibility and stability for force-reflecting bilateral tele-operation through the Internet, we propose a concept for compensation of the delay time for packet transfer based on model based simulation of objects and operator behavior. Moreover, to reduce the delay time and power consumption for the simulation, which is required especially for mobile tele-robot applications, we propose a parallel VLSI processor architecture based on dynamic reconfiguration of various kinds of multiply-adders and its power supply voltage according to the delay time of packet transfer for each sampling period.
Keywords :
Internet; VLSI; adders; delays; integrated circuit design; mobile robots; parallel architectures; power consumption; stability; telerobotics; Internet; delay time compensation; dynamic reconfiguration; force reflecting bilateral teleoperation; mobile telerobot systems; multiply adders; packet transfer; parallel VLSI processor architecture; power consumption; power supply voltages; responsibility; sampling period; stability;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
SICE 2003 Annual Conference
Conference_Location :
Fukui, Japan
Print_ISBN :
0-7803-8352-4
Type :
conf
Filename :
1324284
Link To Document :
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