A Formal Transparency Framework for Validation of Real-Time Discrete-Event Control Requirements Modeled by Timed Transition Graphs

In control of discrete-event systems, translating natural language control requirements into formal specifications in computable graphical form can be error prone, and system designers are often confronted with the longstanding problem of uncertainty in specification formalization, namely: How do we know that such a formalized specification is the one intended? This necessitates specification validation, i.e., manual inspection of the specification´s graphical structure to clarify if it formalizes the intended requirement. The uncertainty is compounded in the specification formalization for timed discrete-event systems (TDESs) as timed transition graphs (TTGs), where real-time behavior also needs to be correctly specified. In the fundamental control framework of TDESs, a TTG prescribes a timed regulation of logical behavior restricting a TDES to some timed event-transition sequences. To help validate specification TTGs, we develop a new specification concept of TTG transparency. Our concept formulation embodies the essence of “summarizing” a specification TTG´s transition sequences for a TDES, to highlight intermittent transitions essential or relevant for comprehending the specification´s nontrivial timed restrictions. The transparency concept governs the reconstruction of a specification TTG into a transparent one. We investigate the problem of maximizing the transparency of specification TTGs for TDESs and show that it is NP-hard. We then develop a polynomial time algorithm for computing a highly transparent TTG. Through two examples, we show that the transparent TTG computed may support specification validation.