Joint graph-decoder design of IRA codes on scalable architectures [LDPC codes]

Channel coding is an important building block in communication systems since it ensures the quality of service. Irregular repeat-accumulate (IRA) codes belong to the class of low-density parity-check (LDPC) codes and even outperform the recently introduced turbo-codes of current communication standards. The advantage of IRA codes over LDPC codes is that they come with a linear-time encoding complexity. IRA codes can be represented by a Tanner graph with arbitrary connections between nodes of given degrees. The implementation complexity of IRA decoders is dominated by the randomness of these connections. In this paper, we present a scalable partly parallel IRA decoder architecture. We present a joint graph-decoder design to parallelize IRA codes which can be efficiently processed by this decoder without any RAM access conflicts. We show design examples of these IRA codes which outperform the UMTS turbo-code by 0.2 dB.