6-bit low power low area frequency modulation based flash ADC

This paper presents a 6-bit frequency modulation based ADC design. The demonstrated design yields a device that uses less than 10% of the power of comparable designs. In addition, this architecture provides a simple and logical way to trade sampling rate for accuracy. The presented device has a power consumption of 30mW while operating at approximately 1.05 GSample/sec with an INL and DNL values of 0.23 and 0.4/-0.3 LSB respectively. The design has been implemented in a 1.8 volt 0.18μm CMOS process.