A 50-MHz CMOS quadrature charge sampling circuit with 66 dB SFDR

The quadrature charge sampling circuit realization in 0.35μm CMOS is presented. The circuit performs complex band-pass filtering for a real-valued 50-MHz IF input signal providing 18 dB of inherent anti-aliasing rejection and downconverters it into baseband quadrature (I/Q) components by subsampling. The measured 3rd-order input intercept-point (IIP₃) is +25 dBV at 50 MHz, while the spurious-free dynamic range (SFDR) is more than 66 dB up to 100 MHz operating frequency. The power consumption without output buffers is 30 mW from a 3.3 V supply.