DocumentCode
417970
Title
An alternative DFT methodology to test high-resolution ΣΔ modulators
Author
Escalera, S. ; García-González, J.M. ; Guerra, O. ; de la Rosa, J.M. ; Medeiro, F. ; Pérez-Verdú, B. ; Rodríguez-Vázquez, A.
Author_Institution
Instituto de Microelectron. de Sevilla, Spain
Volume
1
fYear
2004
fDate
23-26 May 2004
Abstract
In this paper, a DFT methodology to test high-resolution ΣΔ modulators (ΣΔM) is introduced. The aim of the proposal is to reduce the test time required to conventional methodologies without degrading the accuracy of the results. A detailed description of the additional circuitry needed to perform these tests is presented as well as some initial simulation results to show the utility of the approach.
Keywords
circuit simulation; circuit testing; sigma-delta modulation; DFT methodology; high-resolution ΣΔ modulators; test time reduction; Circuit faults; Circuit simulation; Circuit testing; Degradation; Delta modulation; Fault detection; Performance evaluation; Proposals; System testing; Time measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on
Print_ISBN
0-7803-8251-X
Type
conf
DOI
10.1109/ISCAS.2004.1328180
Filename
1328180
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