DocumentCode
417975
Title
An on-chip DNL estimation and reconfiguration for improved linearity in current steering DAC
Author
Rafeeque, K. P Sunil ; Vasudevan, Vinita
Author_Institution
Dept. of Electr. Eng., Indian Inst. of Technol., Chennai, India
Volume
1
fYear
2004
fDate
23-26 May 2004
Abstract
This paper proposes a reconfigurable current steering DAC. It uses an on-chip error estimation. The INL is tuned by optimizing switching sequence. A DAC is designed and fabricated using 0.35μm CMOS technology. The INL improvement is verified both in simulation and actual hardware.
Keywords
CMOS integrated circuits; circuit optimisation; circuit simulation; current-mode circuits; digital-analogue conversion; error compensation; system-on-chip; 0.35 microns; CMOS technology; INL improvement; linearity improvements; on-chip DNL estimation; on-chip error estimation; reconfigurable current steering DAC; switching sequence; CMOS technology; Circuits; Digital-analog conversion; Error analysis; Frequency conversion; Hardware; Linearity; Manufacturing; Switches; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on
Print_ISBN
0-7803-8251-X
Type
conf
DOI
10.1109/ISCAS.2004.1328186
Filename
1328186
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