A 1-V 400MS/s 14bit self-calibrated CMOS DAC with enhanced dynamic linearity

A 1-V CMOS current steering digital to analog converter with enhanced static and dynamic linearity is presented. The 14-bit static linearity is achieved by a background analog self calibration technique which is suitable for low voltage applications and does not require error measurement and correction circuits. The improved dynamic linearity at high frequencies, a low power track/attenuate output stage is used at the DAC output. Integral and differential nonlinearities of the proposed DAC corresponding to a 14-bit specification are less than 0.35LSB and 0.25LSB, respectively. The DAC is functional up to 400MS/s with SFDR better than 71dB in the Nyquist band. The circuit has been designed and simulated in a standard 0.18μm CMOS technology.