A low-voltage low sensitivity sinusoidal VCO for DPLL realizations

A quasi-sinusoidal linearly tunable OTA-C VCO built with triode-region transconductors is presented. Oscillation upon power-on is ensured by RHP poles associated with gate-drain capacitances of OTA input devices. Since the OTA nonlinearity stabilizes the amplitude, the oscillation frequency f₀ is first-order independent of V_DD, making the VCO adequate to mixed-mode designs. A range of simulations attests the theoretical analysis. As part of a DPLL, the VCO was prototyped on a 0.8μm CMOS process, occupying an area of 0.15mm². Nominal f₀ is 1 MHz, with K_VCO=8.4KHz/mV. Measured sensitivity to V_DD is below 2.17, while phase noise is -86dBc at 100 kHz offset. The feasibility of the VCO for higher frequencies is verified by a redesign based on a 0.35μm CMOS process and V_DD=3.3V, with a linear frequency-span of 13.2 MHz-61.5 MHz.