Fast implementation of a linearity test approach for high-resolution ADCs using non-linear ramp signals

The bottleneck of linearity test for high-resolution ADCs lies in the design and manufacturing of fast and stationary signal generators with performance much better than the specification of ADCs under test. Recently a cost-effective approach was proposed for precision ADC linearity test using low-linearity but easy-to-generate ramp signals. This approach relaxed the linearity requirements on the signal generator and maintained high test accuracy by employing a stimulus error identification and removal algorithm. In this paper, a reduced-density interleaved sampling scheme is proposed for the new approach to cut down the data collection time and guarantee the new approach´s robustness to the environmental non-stationary. Theoretical analyses and simulation results show that with the discussed sampling scheme, the test time of the original approach can be reduced by nearly a factor of two and 16-bit test accuracy can be achieved by using 7-bit linear ramp signals, which is comparable to the performance of the original ADC test approach.