Title :
A 32 × 32 four layer reaction-diffusion CNN chip
Author :
Shi, Bertram E. ; Luo, Billow Tao
Author_Institution :
Dept. of Electr. & Electron. Eng.,, HKUST, Hong Kong, China
Abstract :
This paper describes a 32 × 32 four layer neural network chip that exhibits spatially organized patterns of activity, which are formed by reaction-diffusion. The chip was fabricated in 0.5μm CMOS n-well process. Measured patterns consist of alternating regions of high and low activity with a preferred width, but no preferred orientation. This chip is an ideal real-time substrate for studying the spatio-temporal dynamics and applications of reaction-diffusion, since it can be characterized experimentally, theoretically and through simulation. It settles to steady state patterns within several hundred microseconds and dissipates 10.45mW.
Keywords :
CMOS integrated circuits; cellular neural nets; neural chips; pattern formation; pattern recognition; reaction-diffusion systems; 0.5 micron; 10.45 mW; CMOS n-well process; CNN chip; neural network chip; reaction-diffusion; real-time substrate; spatially organized patterns; spatio-temporal dynamics; Capacitors; Cellular neural networks; Cloning; Equations; Feeds; Integrated circuit interconnections; Mirrors; Output feedback; State feedback; Voltage;
Conference_Titel :
Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on
Print_ISBN :
0-7803-8251-X
DOI :
10.1109/ISCAS.2004.1328682