Adaptive LMS processing architectures employing frequency domain sub-convolution

This paper provides an overview of a low-complexity, parameterized, and discrete-time processing architecture for realizing a frequency domain least-mean squares (LMS) complex equalizer by J. Proakis (1995). The realization results in lower complexity implementation in digital very large scale integrated (VLSI) circuits. The architecture incorporates a lossless sub-convolution method, digital vector processing, specialized FFT-IFFT hardware architectures, and the discrete Fourier transform-inverse discrete Fourier transform (DFT-IDFT) overlap and save filter method by A.V. Oppenheim and R.W. Schafer (1989). A key property of the new architecture is that the equalizer tap length may be chosen completely independently of the FFT-IFFT lengths and input data block lengths. Theoretically unlimited tap lengths are possible with short FFT-IFFT pairs. It will be demonstrated that the new parallel architecture is very well suited for processing multi-Gbps digital communication data rates with relatively low speed CMOS hardware.