Title :
Characterization of a 16-bit threshold logic single-electron technology adder
Author :
Sulieman, M. ; Beiu, V.
Author_Institution :
Sch. of Electr. Eng. & Comput. Sci., Washington State Univ., Pullman, WA, USA
Abstract :
Single electron technology (SET) is one of the future technologies distinguished by its small and low-power devices. SET also provides simple and elegant solutions for threshold-logic gates (TLGs). This paper presents the design of an optimal TLG adder implemented in SET. This 16-bit Kogge-Stone style adder was fully designed and simulated using a Monte Carlo simulator. The simulation results give a quantitative estimate of both the delay and the power dissipation of the adder. The characteristics of our adder are compared with recent results estimating the energy-delay characteristics of advanced CMOS adders.
Keywords :
CMOS logic circuits; Monte Carlo methods; adders; circuit simulation; logic gates; single electron devices; threshold logic; 16 bit; CMOS adders; Kogge-Stone style adder; Monte Carlo simulator; delay estimation; energy-delay characteristics; low-power devices; optimal TLG adder; power dissipation; single-electron technology adder; small devices; threshold-logic gates; Adders; CMOS technology; Circuits; Computer science; Costs; Delay estimation; Electrons; Logic devices; Monte Carlo methods; Power dissipation;
Conference_Titel :
Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on
Print_ISBN :
0-7803-8251-X
DOI :
10.1109/ISCAS.2004.1328838
