• DocumentCode
    418291
  • Title

    A high throughput limited search trellis decoder for convolutional code decoding

  • Author

    Zhang, Tong

  • Author_Institution
    Dept. of Electr. Comput. & Syst. Eng., Rensselaer Polytech. Inst., Troy, NY, USA
  • Volume
    4
  • fYear
    2004
  • fDate
    23-26 May 2004
  • Abstract
    Due to the lack of operational parallelism and structured data storage/retrieval, limited search trellis decoding algorithms have been traditionally ruled out for applications demanding high throughput convolutional code decoding. Among various limited search algorithms, the T-algorithm performs breadth-first limited search and has good potential for parallel decoding. In this paper, we propose two techniques at the algorithm and VLSI architecture levels for the T-algorithm to improve the decoding parallelism and tackle the data storage/retrieval problem, which enables the high throughput path-parallel T-algorithm decoder VLSI implementation. This work provides a vehicle for exploiting the merits of the T-algorithm, i.e., low computational complexity that is adaptive to the channel distortion, in high throughput applications.
  • Keywords
    VLSI; Viterbi decoding; computational complexity; convolutional codes; information retrieval; parallel algorithms; trellis codes; VLSI architecture level; channel distortion; computational complexity; convolutional code decoding; data storage-retrieval problem; limited search trellis decoding algorithms; parallel T-algorithm decoder VLSI implementation; parallel decoding; Computational complexity; Computer architecture; Convolutional codes; Decoding; Information retrieval; Memory; Parallel processing; Throughput; Vehicles; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on
  • Print_ISBN
    0-7803-8251-X
  • Type

    conf

  • DOI
    10.1109/ISCAS.2004.1328969
  • Filename
    1328969