A novel memoryless AES cipher architecture for networking applications

In this paper, we present a novel fast S-box algorithm without lookup table method, and novel fast optional hardware architecture for MixColumn and Inverse MixColumn module with only 5 XOR gate delay. We use on-the-fly key schedule architecture for both encryption and decryption. Furthermore, we implement a memoryless AES cipher with proposed S-box architecture and fast MixColumn and Inverse MixColumn module by adopting a pipeline method to obtain high throughput as 1.454 Gbits/sec under 125 MHz using 0.25 m CMOS technology and the hardware cost is about 80 K gate counts. According to our knowledge, our hardware architecture is the first memoryless AES cipher including encryption and decryption function.