Title :
Shunt-peaking in MCML gates and its application in the design of a 20 Gb/s half-rate phase detector
Author :
Bui, Hung Tien ; Savaria, Yvon
Author_Institution :
Ecole Polytech. de Montreal, Que., Canada
Abstract :
This paper presents the techniques of shunt-peaking and active shunt-peaking as methods that can be used in the design of MCML gates. The use of these techniques opens the door to the design of high-speed gates that operate at frequencies where conventional MCML gates cease to function. To prove the concept, a half-rate linear phase detector was designed and submitted for fabrication using 0.18 μm CMOS technology.
Keywords :
CMOS logic circuits; current-mode logic; high-speed integrated circuits; logic design; phase detectors; 0.18 micron; 20 Gbit/s; CMOS technology; MCML gates design; active shunt-peaking; half rate linear phase detector; high-speed gates; Attenuation; CMOS technology; Cutoff frequency; Detectors; Digital circuits; Low pass filters; Phase detection; Power harmonic filters; Shape; Transceivers;
Conference_Titel :
Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on
Print_ISBN :
0-7803-8251-X
DOI :
10.1109/ISCAS.2004.1329017
