A low-power crosstalk-insensitive signaling scheme for chip-to-chip communication

Increasing demand for high-speed inter-chip interconnects requires faster links that consume less power. The Shannon limit for the capacity of these links is at least an order of magnitude higher than the data rate of the current state-of-the-art designs. A novel signaling scheme is proposed that can provide 3 dB coding gain. This signaling scheme is significantly less sensitive to crosstalk, inter-symbol interference and residual reflection compared to the ordinary binary signaling scheme. Moreover, a low-complexity architecture for high-speed implementation of this method is proposed. Finally, an extension of this scheme is presented, which shows better performance at the expense of adding more complexity.