Modeling, design and characterization of a new low jitter analog dual tuning LC-VCO PLL architecture

Author

Nonis, Roberto ; Dalt, Nicola Da ; Palestri, Pierpaolo ; Selmi, Luca

Author_Institution

DIEG, Udine Univ., Italy

Volume

4

fYear

2004

fDate

23-26 May 2004

Abstract

This paper describes the modeling, design and characterization of a low jitter 2.4 GHz LC-VCO PLL architecture realized in a standard 0.12 μm CMOS technology. It features very low VCO gain for noise rejection and it is equipped with an automatic analog calibration of the VCO curve. Measurements show the integrated jitter to be 0.74 ps, that is 43% lower with respect to a standard PLL topology which has same bandwidth and same output frequency range, build for comparison on the same wafer. The circuit area is 0.7 mm² (less then 1% larger than the reference PLL) and the power consumption is 32 mW (1% higher).

Keywords

CMOS analogue integrated circuits; UHF integrated circuits; UHF oscillators; circuit tuning; integrated circuit layout; integrated circuit modelling; jitter; network topology; phase locked loops; phase noise; power consumption; voltage-controlled oscillators; 0.12 micron; 0.74 ps; 2.4 GHz; 32 mW; CMOS technology; PLL topology; automatic analog calibration; circuit area; low jitter analog dual tuning LC-VCO PLL architecture; noise rejection; output frequency range; power consumption; CMOS technology; Calibration; Circuit topology; Frequency measurement; Integrated circuit measurements; Jitter; Measurement standards; Phase locked loops; Semiconductor device modeling; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on

Print_ISBN

0-7803-8251-X

Type

conf

DOI

10.1109/ISCAS.2004.1329063

Filename

1329063