Digital controlled analog architecture for DCT and DST using capacitor switching

This paper describes a sampled analog architecture, for computing DCT or DST, using switched capacitor principle with capacitance switching. The input sample stream is applied to an array of capacitors and multiplied by all the DCT/DST coefficients concurrently using capacitor ratios. These capacitors are switched properly with the help of a switching matrix, to realize switched capacitor integrators for performing necessary addition/subtraction. Proposed architecture simple, regular with lower gate count may be used for online computations.