A new parallel architecture for low power linear feedback shift registers

Low power dissipation is very critical in today´s electronic designs. Components which are widely used in design, such as sequence generators like linear feedback shift registers (LFSR), should consume as little power as possible. Two recent works on parallel architecture of LFSR, one by M. Lowy and another by M.E. Hamid and C.I.H. Chen, have reduced dynamic power consumption significantly compared to the conventional architecture and showed the way to generate multiple outputs. In this paper we propose design improvements on these parallel architectures. The proposed method reduces dynamic power dissipation significantly, simplifies design process for single and multiple output generation, and eliminates the need of some hardware.