Power-aware implementation of ASIC/SOC in 0.13 micron CMOS technology

In this paper, we demonstrate that basic implementation choices can have an order of magnitude of difference in the final power dissipation of the cutting-edge ASIC/SOC designs, and outline a basic checklist for power-aware implementation in deep sub-micron processes. We analyze the significant impact of 1) library choices, 2) register implementation, 3) tools utilization and 4) micro-architectural choices on dynamic power dissipation. We demonstrate that ASIC/SOC designers can achieve significant power reduction without resorting to full-custom techniques by following power-aware implementation prescriptions. We report eight-fold dynamic power reduction and five-fold clock power reduction on CMOS implementation of an adaptive processor IC in 0.13 μm TSMC technology.