An asynchronous SOVA decoder for wireless communication application

Author

Chan, Wing-Kin ; Choy, Chiu-Sing ; Chan, Cheong-Fat ; Pun, Kong-Pang

Author_Institution

Dept. of Electron. Eng., Chinese Univ. of Hong Kong, Shatin, China

Volume

2

fYear

2004

fDate

23-26 May 2004

Abstract

This paper presents a novel asynchronous architecture for a Soft-Output Viterbi Algorithm (SOVA) decoder. This architecture is based on two-step SOVA and asynchronous circuit design. Novel asynchronous traceback structure allows the majority of the data to be static in memory to reduce switching activity and power consumption. This architecture also minimizes the read-write operation of memory. We have designed an asynchronous architecture for SOVA decoder for low power wireless communication applications. This work shows an asynchronous implementation of SOVA decoder running at 2M symbol/s at 6.23 mW, which is suitable in wireless communication such as 3G handsets.

Keywords

3G mobile communication; Viterbi decoding; asynchronous circuits; low-power electronics; mobile handsets; power consumption; switching circuits; 3G handset; 6.23 mW; asynchronous SOVA decoder; asynchronous circuit design; power consumption; read-write operation; soft output Viterbi algorithm decoder; switching activity; traceback structure; two step SOVA decoder; wireless communication; Asynchronous circuits; Clocks; Concatenated codes; Convolutional codes; Iterative decoding; Maximum likelihood decoding; Pipelines; Turbo codes; Viterbi algorithm; Wireless communication;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on

Print_ISBN

0-7803-8251-X

Type

conf

DOI

10.1109/ISCAS.2004.1329322

Filename

1329322