Low complexity digital PLL for instant acquisition CDR

A novel digital circuit is presented which, given one asynchronous training pulse, performs reliable clock and data recovery (CDR) on a bit-stream at rates up to 1.3 Ghz/Gbps. The circuit requires no analog components and is suitable for implementation on standard-cell ASICs or, at a reduced speed, on FPGAs. Unlike other digital PLLs, it does not oversample or use DSP arithmetic. It therefore consumes little area and power, but maintains range and stability. In one embodiment, in 0.18 μm, the circuit immediately locks to symbol rates from 1.3 Ghz - 420 Mhz, consumes 260 gates, insignificant static power, and less than 2 mW at 1 Ghz and full voltage.