Title :
A programmable base 2D-LNS MAC with self-generated look-up tables
Author :
Zhang, W. ; Jullien, G.A. ; Dimitrov, V.S.
Author_Institution :
Dept. Electr. & Comput. Eng., Calgary Univ., Alta., Canada
Abstract :
This paper presents a new architecture for a programmable second base 2-dimensional logarithmic number system (2D LNS) Multiply Accumulator Cell (MAC) using DRAMs to store the conversion look-up tables (LUTs). It uses a direct mapping from non-binary exponents to binary format with a 50% reduction in DRAM size compared to a recently reported architecture. With a simple modification of the DRAM data loading structure, each MAC can build its own LUT specific to the non-binary exponents of 2D-LNS coefficients in a pipelined data flow. This results not only in a considerable reduction of DRAM size, but also in the elimination of adders normally required for computing non-binary exponents in a data filtering channel.
Keywords :
DRAM chips; FIR filters; memory architecture; multiplying circuits; pipeline arithmetic; table lookup; two-dimensional digital filters; DRAM; adder; data filtering channel; data loading structure; direct mapping; dynamic random access memory; multiply accumulator cell; nonbinary exponents; pipelined data flow; programmable logarithmic number system; second base logarithmic number system; self generated look up tables; two dimensional logarithmic number system; Adders; Arithmetic; Digital signal processing; Filtering; Finite impulse response filter; Hardware; Laboratories; Multidimensional systems; Random access memory; Table lookup;
Conference_Titel :
Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on
Print_ISBN :
0-7803-8251-X
DOI :
10.1109/ISCAS.2004.1329390