Sampled analog architecture for DCT and DST

Author

Mal, Ashis Kumar ; Basu, Arindam ; Dhar, Anindya Sundar

Author_Institution

Dept. of Electron. & Electr. Commun. Eng., IIT, Kharagpur, India

Volume

2

fYear

2004

fDate

23-26 May 2004

Abstract

This paper describes an analog sampled data architecture, for computing either DCT or DST alternatively, using switched capacitor circuit and a resistor-string. The input samples are multiplied by all the DCT/DST coefficients concurrently using the resistor-string, and then switched properly with the help of a switching matrix, to different integrators for performing necessary addition/subtraction. The architecture may also be used for computing inverse transforms. Proposed architecture is simple, regular and can be used for online computations with moderate accuracy.

Keywords

analogue multipliers; discrete cosine transforms; integrating circuits; sampled data circuits; switched capacitor networks; analog multiplier; analog sampled data architecture; discrete cosine transform; discrete sine transform; integrators; inverse transform computation; online DCT computations; online DST computations; resistor string; switched capacitor circuit; switching matrix; Analog computers; Capacitors; Computer architecture; DH-HEMTs; Data engineering; Discrete cosine transforms; Discrete transforms; Image coding; Switches; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on

Print_ISBN

0-7803-8251-X

Type

conf

DOI

10.1109/ISCAS.2004.1329399

Filename

1329399