A distributed arithmetic online rotator for signal processing applications

A rotation algorithm is presented which uses distributed arithmetic to re-arrange a complex rotation into a form more suited to FPGA implementation. The algorithm uses precompiled sine values in the two´s complement number system and creates partial results in the redundant binary signed digit (BSD) (see inbid., A. Avizienis,1961) number system. Partial results are summed to produce output digits on-line in BSD. A bit-serial architecture is presented which produces a favorable foot-print and is well suited to working with wide input/output signal processing systems such as beam-formers (K. E. Thomenius, 1996). High throughput is maintained despite the bit-serial approach by utilizing the highly parallel nature of beam-forming.