DocumentCode
419366
Title
A fast and well-structured multiplier
Author
Kang, Jung-Yup ; Gaudiot, Jean-Luc
Author_Institution
Dept. of Electr. Eng., Southern California Univ., CA, USA
fYear
2004
fDate
31 Aug.-3 Sept. 2004
Firstpage
508
Lastpage
515
Abstract
The performance of multiplication is crucial for multimedia applications such as 3D graphics and signal processing systems which depend on extensive numbers of multiplications. Previously reported multiplication algorithms mainly focus on rapidly reducing the partial products rows down to final sums and carries used for the final accumulation. These techniques mostly rely on circuit optimization and minimization of the critical paths. In this paper, an algorithm to achieve fast multiplication in two´s complement representation is presented. Indeed, our approach focuses on reducing the number of partial product rows. In turn, this directly influences the speed of the multiplication, even before applying partial products reduction techniques. Fewer partial products rows are produced, thereby lowering the overall operation time. This results in a true diamond-shape for the partial product tree which is more efficient in terms of implementation.
Keywords
digital arithmetic; multiplying circuits; 3D graphics; circuit optimization; critical paths minimization; fast multiplier; multimedia applications; partial product tree; partial products reduction; signal processing systems; twos complement representation; well-structured multiplier; Adders; Algorithm design and analysis; Circuit optimization; Encoding; Graphics; Minimization; Multimedia systems; Signal processing; Signal processing algorithms; Tree graphs;
fLanguage
English
Publisher
ieee
Conference_Titel
Digital System Design, 2004. DSD 2004. Euromicro Symposium on
Print_ISBN
0-7695-2203-3
Type
conf
DOI
10.1109/DSD.2004.1333319
Filename
1333319
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