A novel amplifier linearization technique using an anti-parallel reconfigurable transistor (ART) pair

A new amplifier linearization methodology using an anti-parallel reconfigurable transistor (ART) pair is proposed. Unlike conventional linearization methods in which only one technique is employed, our ART method utilizes all terminals of an additional transistor and provides a unified pre-, post- and cubic-polynomial distortion technique for performance enhancement. Experimental results reveal a 42 dB reduction for the third-order intermodulation distortion (IMD3) and 15 dB for the fifth-order (IMD5) at 2.1 GHz operation band. The input 1-dB gain compression point and phase distortion have been improved effectively up to 8 dB and 15°, respectively, under a 5-V operation voltage. Meanwhile, the proposed approach demonstrates a peak power added efficiency (PAE) of 61% with 16 dB transducer gain and 21 dBm output power for a single stage low-power SiGe BJT transistor. The adjacent channel power ratio (ACPR) is maintained over -45 and -60 dBc for a W-CDMA and PHS modulated signal, respectively, under a wide range of output power.